This invention relates to a driver of a plasma display panel (PDP).
Plasma displays are display devices using a light emission phenomenon caused by a discharge in gas. Screens of the plasma displays, that is, plasma display panels (PDPs) have advantages in upsizing, slimming-down, and widening of viewing angles over other display devices. PDPs are broadly divided into DC and AC types that operate on DC and AC pulses, respectively. The AC-type PDPs have, in particular, higher brightness and a simpler structure. Accordingly, the AC-type PDPs are suitable for mass production and improvement in a high pixel resolution, and therefore, extensively used.
An AC-type PDP comprises, for example, the three-electrode surface-discharge type structure. See, for example, Published Japanese patent application 2004-13168 gazette. In the structure, address electrodes are arranged on the rear substrate in the vertical direction of the panel, and sustain and scan electrodes are alternately arranged on the front substrate in the horizontal direction of the panel. In general, the scan electrodes separately allow individual potential changes, and the address electrodes do so.
A discharge cell is installed at the intersection of an adjacent pair of sustain and scan electrodes and an address electrode. On the surface of the discharge cell, a layer of dielectric material (a dielectric layer), a layer protecting the electrodes and the dielectric layer (a protection layer), and a layer including phosphor (a phosphor layer) are laminated. The inside of the discharge cell is filled with gas. The gas molecules ionize and emit ultraviolet rays when the applications of voltage pulses between the sustain, scan, and address electrodes cause electric discharges in the discharge cells. The ultraviolet rays excite the phosphors on the surfaces of the discharge cell, and then, cause them to emit fluorescence. Thus, the discharge cells glow.
A PDP driver controls the potentials of the sustain, scan, and address electrodes under the ADS (Address Display-period Separation) scheme. The ADS scheme is a kind of the sub-field scheme where one field of image is divided into a plurality of sub-fields. Each sub-field includes reset, address, and sustain periods. Under the ADS scheme, in particular, the three periods are provided in common for all the discharge cells of a PDP. See, for example, Published Japanese patent application 2004-13168 gazette.
During the reset period, a reset voltage pulse is applied between the sustain and scan electrodes. Thereby, wall charges are evened among all the discharge cells.
During the address period, scan voltage pulses are applied to the scan electrodes in sequence, and address voltage pulses are applied to some of the address electrodes. The address electrodes to be provided with the address voltage pulses are selected based on the video signal received from the outside. A discharge in gas occurs in the discharge cell located at the intersection of the scan electrode provided with the scan voltage pulse and the address electrode provided with the address voltage pulse. As a result of the discharge, wall charges accumulate on the surfaces of the discharge cell.
During the sustain period, the sustain voltage pulses are periodically and simultaneously applied to all the pairs of the sustain and scan electrodes. At that time, in the discharge cells where the wall charges have accumulated during the address period, the gas discharges are sustained, and accordingly, the discharge cells glow. The durations of the sustain periods vary among the sub-fields, and therefore, a light emission time per field of the discharge cell, that is, the brightness of the discharge cell is adjusted by the selection of a sub-field in which the discharge cell should glow.
FIG. 24 is an equivalent circuit diagram showing scan and sustain electrode driver sections 110 and 120 of a conventional PDP driver and a PDP 20. See, for example, Published Japanese patent application 2003-15600 gazette. Here, the equivalent circuit of the PDP 20 is represented only by a stray capacitance-Cp between the sustain and scan electrodes X and Y, which is hereafter referred to as a panel capacitance of the PDP 20. A path of the current flowing through the PDP 20 at the discharges in the discharge cells is omitted.
In the reset, address, and sustain periods, the potentials of the scan, sustain, and address electrodes Y, X, and A of the PDP 20 change as follows. See FIG. 25. The hatched areas shown in FIG. 25 represent the ON periods of the switching devices Q1, Q2, QS, QR1, QR2, SA1, SA2, SC1, SC2, Q1X, and Q2X, shown in FIG. 24.
During the reset period, in the scan electrode driver section 110, a scan pulse generating section 111 maintains a low side scan switching device SC2 in the ON state. A reset pulse generating section 112 applies a reset voltage pulse through the low side scan switching device SC2 to the scan electrode Y. In the sustain electrode driver section 120, at the same time, a second sustaining pulse generating section 123 applies a reset voltage pulse to the sustain electrode X. Thereby, potentials of the scan and sustain electrodes Y and X change. On the other hand, the address electrode A is maintained at the ground potential (nearly equal to 0).
According to the change of the reset voltage pulse, the reset period is divided into the following six modes I-VI.
<Mode I>
In the scan electrode driver section 110, the first low side sustain switching device Q2, the separation switching device QS, the low side auxiliary switching device SA2, and the low side scan switching device SC2 are maintained in the ON state. In the sustain electrode driver section 120, the second low side sustain switching device Q2X is maintained in the ON state. The remainder of the switching devices are maintained in the OFF state. Thereby, both the scan and sustain electrode Y and X are maintained at the ground potential.
<Mode II>
In the scan electrode driver section 110, the first low side sustain switching device Q2 is turned off, and the first high side sustain switching device Q1 is turned on. Thereby, the potential of the scan electrode Y rises to the potential Vs of the external power supply Es. In the sustain electrode driver section 120, the ON and OFF states of all the switching devices are maintained as they are. Thereby, the sustain electrode X is maintained at the ground potential.
<Mode III>
In the scan electrode driver section 110, the separation switching device QS is turned off, and the high side ramp wave generating section QR1 is turned on. Thereby, the potential of the scan electrode Y rises at a constant rate from the potential Vs of the external power supply Es to the upper limit Vr of the reset voltage pulse. In the sustain electrode driver section 120, the ON and OFF states of all the switching devices are maintained as they are. Thereby, the sustain electrode X is maintained at the ground potential. Thus, the voltages applied to all the discharge cells of the PDP 20 uniformly rise to the upper limit Vr of the reset voltage pulse. Thereby, uniform wall charges accumulate in all the discharge cells of the PDP 20.
The upper limit Vr of the reset voltage pulse must be high enough for making wall charges uniform in all the discharge cells of the PDP 20 in the reset period. Accordingly, the upper limit Vr of the reset voltage pulse is set, in general, higher than the potential Vs of the external power supply Es.
In mode III, the potential exceeds the potential Vs of the external power supply Es on a path from the separation switching device QS through the low side scan switching device SC2 to the node J of the series connection 1S of the two scan switching devices SC1 and SC2. See FIG. 24. On the other hand, the separation switching device QS is turned off, and the current to flow from the low side scan switching device SC2 to the output terminal J1 of the first sustaining pulse generating section 113 (the node between the two sustain switching devices Q1 and Q2) is cut off. Thereby, the reset voltage pulse rises reliably to the upper limit Vr, without being clamped by the body diode of the first high side sustain switching device Q1 to the potential Vs of the external power supply Es.
<Mode IV>
In the scan electrode driver section 110, the high side ramp wave generating section QR1 is turned off, and the separation switching device QS is turned on. Thereby, the potential of the scan electrode Y falls to the potential Vs of the external power supply Es. In the sustain electrode driver section 120, the ON and OFF states of all the switching devices are maintained as they are. Thereby, the sustain electrode X is maintained at the ground potential.
<Mode V>
In the scan electrode driver section 110, the ON and OFF states of all the switching devices are maintained as they are. Thereby, the scan electrode Y is maintained at the potential Vs of the external power supply Es. In the sustain electrode driver section 120, the second low side sustain switching device Q2X is turned off, and the second high side sustain switching device Q1X is turned on. Thereby, the potential of the sustain electrode X rises to the potential Vs of the external power supply Es.
<Mode VI>
In the scan electrode driver section 110, the first high side sustain switching device Q1 is turned off, and the low side ramp wave generating section QR2 is turned on. Thereby, the potential of the scan electrode Y falls at a constant rate to the ground potential. In the sustain electrode driver section 120, the ON and OFF states of all the switching devices are maintained as they are. Thereby, the sustain electrode X is maintained at the potential Vs of the external power supply Es. Accordingly, the voltage opposite in polarity to the voltages applied in the modes II-V is applied to the discharge cells of the PDP 20. Thereby, the wall charges are uniformly eliminated and evened in all the discharge cells.
During the address period, in the sustain electrode driver section 120, the second high side sustain switching device Q1X is maintained in the ON state. The remainder of the switching devices are maintained in the OFF state. Thereby, the sustain electrode X is maintained at the potential Vs of the external power supply Es. In the scan electrode driver section 110, the first low side sustain switching device Q2, the separation switching device QS, and the high side auxiliary switching device SA1 are maintained in the ON state. Accordingly, one end of the series connection 1S of the scan switching devices SC1 and SC2 is maintained at a potential Vp=V1 higher than the ground potential by the voltage V1 of the first constant-voltage source E1 (the potential Vp is hereafter referred to as the upper limit of the scan voltage pulse), and the other end of the series connection 1S is maintained at the ground potential.
At the start of the address period, for all the scan electrodes Y, the high- and low-side scan switching devices SC1 and SC2 are maintained in the ON and OFF states, respectively. Thereby, the potentials of all the scan electrodes Y are uniformly maintained at the upper limit Vp of the scan voltage pulse. Next, the scan electrode driver section 110 changes the potentials of the scan electrodes Y as follows. See the scan voltage pulse SP shown in FIG. 25. When one Y of the scan electrodes is selected, the high- and low-side scan switching devices SC1 and SC2 connected to the scan electrode Y are turned off and on, respectively. Thereby, the potential of the scan electrode Y falls to the ground potential. When the scan electrode Y is maintained at the ground potential for a predetermined time, the low and high side scan switching device SC2 and SC1 connected to the scan electrode Y are turned off and on, respectively. Thereby, the potential of the scan electrode Y rises to the upper limit Vp of the scan voltage pulse. The scan electrode driver section 110 performs the switching operation similar to the above-described one, for the series connections 1S of the scan switching devices SC1 and SC2 connected to the respective scan electrodes one after another. Thus, the scan voltage pulses SP are applied to the respective scan electrodes in sequence.
During the address period, one A of the address electrode is selected based on the video signal received from the outside, and the potential of the selected address electrode A rises to the upper limit Va of the signal voltage pulse for a predetermined time. For example, when the scan voltage pulse SP is applied to one Y of the scan electrodes and the signal voltage pulse Va is applied to one A of the address electrodes, as shown in FIG. 25, the voltage between the scan and address electrodes Y and A is higher than the voltages between other electrodes. Accordingly, an electric discharge occurs in the discharge cell located at the intersection between the scan and address electrodes Y and A. New wall charges accumulate on the surfaces of the discharge cell because of the electric discharge.
During the sustain period, in the scan electrode driver section 110, the scan pulse generating section 111 maintains the low side scan switching device SC2 in the ON state, and the reset pulse generating section 112 maintains the separation switching device QS in the ON state. The first sustaining pulse generating section 113 turns on the two sustain switching devices Q1 and Q2 alternately. Thereby, the potential of the scan electrode Y changes between the potential Vs of the external power supply Es and the ground potential. In other words, the sustaining voltage pulse is applied to the scan electrode Y through the separation and low-side switching devices QS and SC2. At the same time, in the sustain electrode driver section 120, the second sustaining pulse generating section 123 turns on the two sustain switching devices Q1X and Q2X alternately. Thereby, the potential of the scan electrode Y changes between the potential Vs of the external power supply Es and the ground potential. In other words, the sustaining voltage pulse is applied to the sustain electrode X. The sustaining voltage pulses are applied alternately to the scan and sustain electrode Y and X, since the two sustaining pulse generating sections 113 and 123 operate in the opposite phase. See FIG. 25. Thereby, the AC voltage appears between the scan and sustain electrodes Y and X in each discharge cell of the PDP 20. At that time, in the discharge cell where the wall charges have accumulated during the address period, the electric discharge is sustained, and therefore, the light emission occurs.
Two power recovery sections 114 and 124 each include an inductor and a recovery capacitor (not shown). When the potential of the scan electrode Y rises or falls, in the first power recovery section 114, the inductor resonates with the panel capacitance Cp of the PDP 20, and thereby, the electric power is efficiently exchanged between the recovery capacitor and the panel capacitance Cp. Similarly when the potential of the sustain electrode X rises or falls, in the second power recovery section 124, the inductor resonates with the panel capacitance Cp, and the electric power is efficiently exchanged between the recovery capacitor and the panel capacitance Cp. Thus, at the application of the sustaining voltage pulse, reactive power due to the charging and discharging of the panel capacitance is reduced.
For the reduction in power consumption of PDP, lower voltages applied to the sustain, scan, and address electrodes are desirable. For example, the voltage applied to the sustain electrode during the reset and address periods can be reduced when the lower limits of the reset and scan voltage pulses are set lower than the ground potential. Thereby, the power consumption of PDP is reduced without changing the applied voltages to the discharge cells of the PDP.
As shown in FIG. 26, for example, the low side ramp wave generating section QR2 may be connected to an external negative voltage source En (its voltage: −Vn<0) in place of the ground conductor for the purpose of setting the lower limit of the reset voltage pulse lower than the ground potential. See, for example, Published Japanese patent application 2000-293135 gazette. Thereby, in the mode VI of the reset period, the lower limit −Vn of the reset voltage pulse falls below the ground potential, in contrast to FIG. 25.
In such PDP driver, the scan electrode driver section 110 includes another separation switching device QS1. See FIG. 26. During the ON period of the low side ramp wave generating section QR2 (cf. the mode VI shown in FIG. 25), the potential falls below the ground potential in the path from the separation switching device QS1 through the low side scan switching device SC2 to the node J of the two scan switching devices SC1 and SC2. However, the separation switching device QS1 is turned off, and then, the current to flow from the output terminal J1 of the first sustaining pulse generating section 113 to the low side scan switching device SC2 is cut off. Thereby, the reset voltage pulse falls reliably to the negative lower limit −Vn, without being clamped by the body diode of the first low side sustain switching device Q2 to the ground potential.
In conventional PDP drivers as described above, both the reset and sustaining pulse generating sections raise and lower the potentials of the scan electrodes through a common scan switching device, for example, the low side scan switching device SC2. Accordingly, during the reset period, the sustaining pulse generating section must be separated from the scan switching device (for example, the low side scan switching device SC2), in order to prevent the reset voltage pulse from being clamped to the upper or lower limit of the sustaining voltage pulse.
In the conventional PDP driver, the separation switching device is installed between the sustain and scan switching devices. In the example shown in FIG. 24, the separation switching device QS is inserted between the output terminal J1 of the first sustaining pulse generating section 113 and the low side scan switching device SC2, and cuts off a current to flow from the low side scan switching device SC2 to the output terminal J1. In the example shown in FIG. 26, another separation switching device QS1 is inserted between the output terminal J1 of the first sustaining pulse generating section 113 and the low side scan switching device SC2, and cuts off a current to flow opposite to the direction of the above-described current. In other words, the pair of the separation switching devices QS and QS1 constitutes a two-way switch.
During the sustain period, the separation switching device is turned on, and thereby, the sustaining pulse generating section is connected to the scan switching device. During the reset period, the separation switching device is turned off, and thereby, the sustaining pulse generating section is separated from the scan switching device. Thus, the reset voltage pulse rises and falls to the predetermined upper and lower limits, respectively, without being clamped to the upper and lower limits of the sustaining voltage pulse.
During the sustain period, the separation switching device allows currents to flow. The currents are caused by the applications of the sustaining voltage pulses to the PDP, that is, the gas discharges in the discharge cells and the charging and discharging of the panel capacitance. The amount of the current is, in general, larger than the amounts of currents caused by the applications of the other voltage pulses, and accordingly, the reduction in conduction loss at the separation switching devices is important for the reduction in power consumption in the PDP driver. In particular, the ON resistance of the separation switching device must be set sufficiently low. Accordingly, the number or size of the separation switching device is large. As a result, it is difficult to establish the compatibility between reduction in power consumption and improvement in miniaturization.
In the example shown in FIG. 26, the lower limit of the reset voltage pulse is set lower than the ground potential, that is, the lower limit of the sustaining voltage pulse. In that case, the two-way switch had to be composed of the separation switching devices in order to prevent the reset voltage pulse from being clamped to the lower limit of the sustaining voltage pulse. Under that conditions, the number of the separation switching devices further increases, and therefore, prevents both of reduction in conduction loss and improvement in miniaturization.
In the example shown in FIG. 26, in addition, the potentials at the ends of the series connection 1S of the separation switching devices QS and QS1 change within the ranges equal to the amplitudes of the reset and sustaining voltage pulses, respectively. Accordingly, the separation switching device requires a withstand voltage substantially equal to or above the difference between the upper limit of the reset voltage pulse and the lower limit of the sustaining voltage pulse. Therefore, the reduction in ON resistance of the separation switching device is difficult. As a result, it is further difficult to lower the conduction losses at the separation switching devices and improve the miniaturizations of the separation switching devices.